Solid State Drive Primer # 8 - Controller Architecture - Channels and Banks
This article follows the Basic SSD Controller Architecture article. It will focus on the connection between the SSD controller and the NAND flash. There are many NAND configurations in SSD design and it makes a large difference to the SSD’s overall power, performance and cost.
The illustration below shows a common 2.5” SATA III SSD NAND configuration. In this example, there are 8 Channels connected to the NAND chips. For each channel there are 2 Banks of NAND components.
There is a control line which selects either Bank 1 or Bank 2 to be active on the Data/Control Bus for a specific channel. This control line is connected to the Chip Select of each NAND component to enable or disable the component.
Channels refer to the number of flash chips the controller can talk to simultaneously. Low end SSDs usually have 2 or 4 channels; high end SSDs usually have 8 channels, some have 10 channels.
SSD manufacturers can trade off performance vs power consumption by stuffing less channels at time of manufacture. The limitation on more channels is added die size, pin count and power consumption, which all increase the cost.
Each flash chip at the same location in a channel together constitutes a bank. Refer to the diagram above. Each channel can have multiple chips. The limitation on maximum number of chips is a result of pin count/die size/cost considerations.