Poor SSD Controller Design Compromises the Best NAND Memory
Let’s take a look at the three major areas which comprise a solid state drive.
- NAND Memory Type and Trace Width Geometry
- Controller Architecture, Firmware Algorithms
- Physical Construction, Ancillary Components, PCB, etc.
NAND memory is available in several types today. Each has its advantages and disadvantages as shown in the table below.
(SINGLE LEVEL CELL)
|UP TO 70,000 ENDURANCE CYCLES PER PHYSICAL BLOCK||HIGH COST|
(MULTI LEVEL CELL)
|2000 - 3000 ENDURANCE CYCLES PER PHYSICAL BLOCK||MEDIUM COST, ONLY AVAILABLE IN FINER TRACE WIDTHS, SHORT LIFE CYCLE|
(TRI LEVEL CELL)
|LOW COST||AS LOW AS 200 - 300 ENDURANCE PER PHYSICAL BLOCK|
As you can see there are options to fit reliability and cost budgets. With all of these options, it’s no coincidence there is confusion in the market.
The vast majority of the flash storage market is focused on consumer electronics, client PCs and enterprise storage solutions which value performance and cost more than reliability. For this market, TLC NAND based solid state storage systems based on the finest geometry trace width provide the low-cost criteria necessary at the expense of reliability.
The chart below shows the significant differences in the number of raw Endurance cycles per physical block of NAND Flash memory based on NAND Flash type and the Geometry Node of its fabrication.
Two other derivatives of the three main memory types are pSLC and eMLC NAND memory. A future article will dig deeper into these technologies, but a brief explanation is below:
pSLC - Pseudo Single Level Cell - As the pseudo in the name suggests, this is NOT SLC NAND. It is a MLC NAND component being used as 1-bit per cell versus its normal 2-bit per cell operation.
Since only half the capability of each cell is used, only half the total MLC NAND’s capacity is available (ex: 32GB MLC NAND is only usable as 16GB).
Using MLC NAND in the pSLC configuration does NOT make it as reliable as a SLC NAND component. The MLC NAND is made from a much smaller geometry node and has the associated issues with endurance and ECC errors. There is not substantial data to back up pSLC as any more reliable than using the full capacity of the MLC component with 2x the cells to perform wear leveling.
eMLC - Enterprise Multi Level Cell - This is a sorted MLC component which has its endurance increased from typical 2000-3000 cycles to 10,000-20,000 cycles. The tradeoff is a lower data retention of about 30 days as well as a price premium.
Neither the pSLC or eMLC NAND memory has made significant inroads to the Embedded OEM market. They tend to be focused on the Enterprise SSD market in which the SSD acts more like a cache than a long term storage device.
Geometry Node (aka Trace Width) has a profound effect on the endurance of NAND memory cells of all types. Endurance is a key, but not the only factor when considering reliability of NAND devices. As Geometries get smaller, error rates become an increasing issue due to the closer proximity of neighboring cells in the NAND silicon.
Initial testing of MLC NAND and finer trace width SLC NAND memory is ongoing. As the trace widths decrease, reliability decreases as well. We will continue to publish our findings as they become available.
All NAND devices will have errors during use, this is due to a variety of factors - charge leakage, sense amp. errors, disturbance due to noise coupling, device wear out, etc. That's why all flash controllers incorporate ECC hardware to correct these errors on the fly.
ECC hardware has a fixed correction capability; as the device wears out and error rate increases, it will eventually overwhelm the ECC correction capability and cause device failure. Lower error rates are better for long term reliability.