I was recently asked to explain how Cactus can specify >2M Endurance cycles per block for our Industrial Grade Flash Storage products when the underlying SLC NAND flash memory is only rated at 50K to 100K endurance cycles. Here’s my response.
The specification of >2 Million endurance cycles per logical block is an Industry standard specification for Industrial Grade products. It is representative of a calculated endurance per logical block – including ECC, wear leveling and defect management techniques.
It is not representative of the physical block endurance of raw SLC NAND, which varies, from 50K to 100K cycles, depending mainly on trace width generation. See white paper: SLC vs MLC NAND and The Impact of Technology Scaling.
As a side note, Commercial Grade cards rated at 100K logical endurance cycles are using MLC NAND currently with ~3K physical endurance cycles (Consumer cards use TLC NAND with ~300 cycles).
There are a number of techniques to improve the number of logical endurance cycles of the raw SLC NAND components used.
The first of which is Error Checking & Correction (ECC). ECC has the ability to detect and correct, on the fly, up to several or many bits per block. ECC kicks in when the raw NAND component is experiencing correctable errors, which typically occurs after it’s exceeded its rated endurance. By correcting the initial failing bits up to the ECC’s capabilities the life of a particular block of physical memory is extended.
When the abilities of ECC have been exhausted and the physical NAND block can no longer reliably store data, Defect Management Techniques come into play. The “bad” block is replaced by a “spare” block, which comes from an extra "pool" of memory the controller maintains for this purpose.
For Industrial Grade products using the highly reliable SLC NAND, >2% “spares” is typical. For non-Industrial, MLC NAND based products, up to 28% “over-provisioning” is common to make the much lower endurance NAND usable for lower duty cycle applications.
The final endurance improvement technique I’ll discuss here is Wear Leveling. The purpose of wear leveling is to spread the logical writes coming into the flash storage device evenly among the physical NAND blocks.
A properly functioning wear leveling system would not need to replace an exhausted NAND block when there are other blocks which have significant endurance cycles available. A detailed explanation can be found in the following white paper: Wear Leveling – Static, Dynamic and Global.
While many would argue the >2M endurance cycles per logical block specification for Industrial Grade Flash Storage Devices is misleading, it is a data point the industry has adopted to represent Industrial Grade products based on SLC NAND memory. Since this specification is based on assumptions of a generic usage model, the actual logical endurance could be much higher or lower than this number.
To really dig into how a specific Cactus Industrial Grade product would work in your application, we have created the Endurance Models for Cactus Technologies Industrial-Grade Flash Storage Products white paper.